1. Field of the Invention
The present invent-ion generally relates to a broadband sampling gate circuit which may be employed in sampling type oscilloscopes and the like. More specifically, the present invention is directed to such a broadband sampling gate circuit in which waveform distortions in a low frequency region can be corrected for at high precision.
2. Discussion of the Background
In FIG. 1, there is shown a first conventional sampling gate circuit. Referring now to this drawing, operations of this first conventional sampling gate circuit will be described.
Reference numeral 50 indicates a signal source which generates, for instance, a signal having a stepped waveform as a signal to be measured. This stepped signal is supplied via a resistor RO indicative of an internal impedance of this signal source 50, and via an input terminal 56 to a first sampling gate 11.
The first sampling gate 11 includes a switch S11, a resistor R11 indicative of an ON-resistance value when the switch S11 is turned ON, and a capacitor C11 representative of a capacitance value across an element (normally, a diode) employed as a gate element.
When the switch S11 is turned ON only during a short-time period, an amplitude component of the signal to be measured which has been supplied thereto via the resistors R0 and R11 is charged (memorized) into a capacitor C12. This operation is called a "sampling operation". The amplitude component of the signal to be measured, which has been charged into this capacitor C12, is gradually charged, via a resistor R12 having a sufficiently larger resistance than that of the resistor R0 or the resistor R11, to a capacitor C13 equal to both of an input capacitance of an amplifier 51B and a stray capacitance of a wiring pattern. An electron charge stored into the capacitor C13 is discharged by a resistor R13 having a sufficiently larger resistance than that of the resistor R12, and then reset to zero.
It should be noted that since the switch S11 is turned ON for a short time period and then the capacitor C12 is charged, and since the resistance value of the resistor R12 is sufficiently greater than that of the resistor R11, the presence of the resistor R12 gives substantially no effect to the charging operation to the capacitor C12, but this resistor R12 has a buffer function which separates the capacitor C12 from the capacitor C13.
The amplitude component of the signal to be measured, which has been charged into the capacitor C13, is amplified by a differential amplifier 51B, and again sampled by a second sampling gate 55, which is a so-called "stretcher", which is operated after a predetermined time period after the first sampling gate 11 has been turned ON, whereby a sampled output is obtained at an output terminal 59. It should be noted that the input signal applied to the first sampling gate 11 is also supplied to an equivalent network 20 having substantially equal attenuation values and time constants as the sampling network, with respect to the signal to be measured when the switch S11 is turned OFF, which is constructed of the first sampling gate 11, the capacitors C12 and C13, and the resistors R12, R13.
This equivalent network 20 includes an attenuator 25, capacitors C21, C23 and resistors R22, R23. The input signal which is equal to the signal to be measured is supplied from the input terminal 56 to an attenuator 25, and is then supplied via a series connection of a resistor R22 and a capacitor C21 to a parallel connection of a resistor R23 and a capacitor C23.
A signal appearing between terminals of the capacitor C13 is supplied to a positive (+) input terminal of the differential amplifier 51B, whereas a signal appearing between terminals of the capacitor C23 is inputted to a negative (-) input terminal of the differential amplifier 51B.
In the first sampling gate 11, when a time constant defined by a product between the capacitor C12 and a summation of the resistors R0 and R11 becomes small with respect to a time duration that the switch S11 is turned ON, the voltage appearing between the terminals of the capacitor C12 is equal to the voltage value of the signal to be measured during the sampling period. Such an operation state is referred to as a "track hold mode". To the contrary, when the time constant defined by the product of the capacitor C12 and the summation between the resistor R0 and R11 becomes large, the terminal Voltage Of the capacitor C12 is lower than the voltage of the signal to be measured during the sampling operation. Such an operation state is referred to as a "sample hold mode".
In FIG. 2, there are shown waveforms at various circuit portions in the first conventional sampling gate circuit indicated in FIG. 1 when the negative (-) input terminal of the differential amplifier 51B is grounded. For the sake of explanation, these waveforms appear in the case that the waveform of the signal source 50 is a stepped signal in the track hold mode. FIG. 2a represents the stepped waveform of the signal source 50. FIG. 2(b-1) represents that the stepped waveform of the signal source 50 shown in FIG. 2a is sampled when the switch S11 of the first sampling gate 11 is turned ON for a short time period at a time instant indicated by an arrow. Since this sampling operation is performed at a portion where the amplitude of the stepped waveform shown in FIG. 2a is zero, there is no influence in the waveform appearing across the capacitor C12, as shown in FIG. 2(d-1). A short time after the switch S1l is operated (FIG. 2(b-1)), as shown in FIG. 2(c-1), another sampling operation is performed while the second sampling gate 55 is operated. At this time, as shown in FIG. 2(e-1), since no signal appears at the terminals of the capacitor C13, there is no signal waveform on the reproduced waveform shown in FIG. 2(f) which has been reproduced by sampling this signal.
FIG. 2(b-2) indicates such an operation that the switch S11 is operated just before the stepped waveform shown in FIG. a is raised, whereas FIG. 5(c-2) represents such an operation that the second sampling gate 55 is operated just after the stepped waveform shown in FIG. 2a is raised. It should be noted that an electrostatic capacitance, as indicated as the capacitor C11, is present across terminals of a high speed switching diode employed in the first sampling gate 11. As a result, when the stepped waveform shown in FIG. 2a is supplied from the signal source 50, although the switch S11 is turned OFF, the capacitor C12 is charged via the resistor R11 and the capacitor C11, and thus a waveform as shown in FIG. 2(d-2) appears across the terminals of the capacitor C12. A time constant of charge-up operation at this time is defined by a product between the resistor R0 and the series circuit of the capacitor C11 and C12. During this charge-up operation, substantially no current flows through the resistor R12 and this circuit functions as a buffer.
After the capacitor C12 is charged up as shown in FIG. 2(d-2) and the charged electrons have reached their peak value, the capacitor C13 is charged via the resistor R12 and the charged voltage is raised as shown in FIG. 2(e-2). A time constant during this raising period is equal to a product between the resistor R12 and the capacitor C13. The waveform appearing across the terminals of the capacitor C12, shown in FIG. 2(d-2), is also lowered due to the discharge operation via the resistor R12 in connection with the charge-up operation of the capacitor C13. After the capacitor C13 has been charged up, this capacitor C13 is gradually discharged via the resistor R13. Then, since the second sampling gate 55 is operated as shown in FIG. 2(c-2), and the waveform appearing across the terminals of the capacitor C13, shown in FIG. 2(e-2), is sampled, the resultant reproduction waveform is obtained as indicated in FIG. 2(f).
FIG. 2(b-3) represents such a state that the switch S11 is turned ON only for a short time period slightly after the stepped waveform of the signal source 50 shown in FIG. 2a is raised and then the sampling operation is carried out. As shown in FIG. 2(d-3), a waveform across the terminals of the capacitor C12 is equal to that shown in FIG. 2(d-2) until the switch S11 of FIG. 2(b-3) is operated. When the switch S11 is turned ON only for a short time period at the time instant shown in FIG. 2(b-3), and the sampling operation is carried out, the capacitor C12 is charged until the potential of this capacitor C12 becomes a potential equal to the amplitude of the stepped waveform of the signal source 50 shown in FIG. 2a irrelevant of the potential of the capacitor C12 before the sampling operation. Thereafter, since the capacitor C13 is charged via the resistor R12, the waveform appearing across the capacitor C12 is lowered due to the discharge operation as shown in FIG. 2(d-3), and then the waveform appearing across the terminals of the capacitor C13 is increased due to the charge operation as shown in FIG. 2(e-3). Since the resistance value of the resistor R13 is sufficiently larger than that of the resistor R12, the waveform appearing across the terminals of the capacitor C13 shown in FIG. 2(e-3) is reduced due to the discharge operation outside the right hand of this figure. A time constant while the capacitor C13 is charged/discharged is much greater than that when the switch S11 is turned ON within a short time period. Then, at a time instant as shown in FIG. 2(c-3), since the second sampling gate 55 is operated and also the waveform of the capacitor C13 as shown in FIG. 2(e-3) is sampled, the resultant waveform is represented in FIG. 2(f). This reproduced waveform shown in FIG. 2(f) has a waveform distortion, a so-called "blowby" distortion, which is different from the stepped waveform as represented in FIG. 2(a).
The above-described operation is effected in such a case that the negative (-) input terminal of the differential amplifier 51B is grounded, namely there is no equivalent 2(f), there is provided the equivalent network 20. Thus, operations of the equivalent network 20 shown in FIG. 1 will now be explained.
Since amplitudes of the signals sampled by the sampling operations of both the first and second sampling gates 11 and 55 become zero when the sampling operations of the first sampling gate 11 and the second sampling gate 55 are carried out before the stepped waveform of the signal source 50 is raised, the voltages appearing across the terminals of the capacitors C13 and C23 are equal to zero, and further the output from the differential amplifier 51B is equal to zero.
In FIG. 3, there is shown such a case that before the stepped waveform of the signal source 50 (see FIG. 2) is raised up (see FIG. 3a), the switch 11 is operated (see FIG. 3b), whereas after the stepped waveform has been raised, the second sampling gate 55 of FIG. 3(c) is operated. A sampling result by the switch S11 of the first sampling gate 11, as shown in FIG. 3(b), is equal to zero, as represented in FIG. 3(d), of the waveform of the capacitor C12. Thereafter, since the stepped waveform of the signal source 50 shown in FIG. 3(a) is raised, electron charges are charged C11 to the capacitor C12, so that a waveform shown in FIG. 3(d) appears. The electron charges stored in the capacitor C12 are transferred via the buffering resistor R12 to the storage capacitor C13. As a result, the voltage across the terminals of the capacitor C13 are applied to the positive (+) input terminal of the differential amplifier 51B, whereby an exponential waveform appears as shown in FIG. 3(e). Also, the same exponential waveform is outputted from the equivalent network 20 and a voltage across the terminals of the capacitor C23 included in the equivalent network 20 is applied to the negative (-) input terminal of the differential amplifier 51B, and then a waveform shown in FIG. 3(f) is inputted, so that no output signal is derived from the differential amplifier 51B (see FIG. 3g). If this is sampled at the timing of the second sampling gate 55 as shown in FIG. 3(c), a point (corresponding to a point indicated by a round mark in FIG. 3(g)) is indicated on the stepped waveform of the signal source 50 shown in FIG. 3(a).
In FIG. 4, there is shown such a state that after a time period "T" has passed since the stepped waveform of the signal source 50 shown in FIG. 4(a) was raised, the switch S11 shown in FIG. 4(b) and the second sampling gate 55 shown in FIG. 4(c) are operated. When the stepped waveform of the signal source 50 shown in FIG. 4(a) is raised up, the electron charges are transferred to the capacitor C12 so that a first peak waveform as indicated by FIG. 4(d) is produced. A voltage across the terminals of the capacitor C13 has such a waveform shown in FIG. 4(e) under such a state that the capacitor C13 is charged via the resistor R12 having the buffer function by the waveform shown in FIG. 4(d).
On the other hand, since the stepped waveform derived from the signal source 50 as shown in FIG. 4(a) is supplied Via the attenuator 25, capacitor C21 and resistor R22 to a parallel circuit between the capacitor C23 and the resistor R23, a waveform of the voltage across the terminals of the capacitor C23 becomes the same waveform as the voltage across the terminals of the capacitor C13 shown in FIG. 4(e) during time period "T", and as the waveforms shown in FIGS. 4(e) and 4(f) are applied to the differential amplifier 51B, the output derived from the differential amplifier 51B remains zero during the time period "T" as shown in FIG. 4(g). When the sampling operation is carried out by operating the switch S11 shown in FIG. 4(b), the potential at the capacitor C12 is equal to a potential value of the input signal derived from the signal source 50 shown in FIG. 4(e) under operation of the track hold mode. Here, the electron charges stored into the capacitor C12 are transferred to the capacitor C13, so that a waveform portion as shown in FIG. 4(e) appears during a period of "Ts" at the positive (+) input terminal of the differential amplifier 51B.
A signal waveform appearing between the terminals of the capacitor C23 during the time period "Ts" shown in FIG. 4(f) is applied to the negative (-) input terminal of the differential amplifier 51B via the equivalent network 20. A time constant of the signal waveform shown in FIG. 4(f) is equal to that of the signal waveform shown in FIG. 4(e). Since an amplitude of a signal stored in the capacitor C13 becomes large, as shown in FIG. 4(d), in response to the operation of the switch S11 an amplitude of the signal shown in FIG. 4(f) is smaller than that of the signal shown in FIG. 4(e). As a consequence, a signal shown in FIG. 4(g) is obtained from the output of the differential amplifier 51B. However, it is apparent that a component to preventing the input signal shown in FIG. 4(a) from being faithfully reproduced is contained in a signal component (see FIG. 4g) obtained by amplifying a difference between the signal waveforms shown in FIGS. 4(e) and 4(f), namely a difference signal. Therefore, equivalent circuits in various cases from which the equivalent network 20 of FIG. 1 has been removed are represented in FIG. 5, and will now be analyzed as follows.
In FIG. 5, resistance values of the resistors R12, R13 are indicated by R.sub.12, R.sub.13 ; capacitance values of the capacitors C13, C15 are denoted by C.sub.13, C.sub.15 ; and voltages of the equivalent voltage sources V1 to V14, V21 to V23 are represented by V.sub.11 to V.sub.14, V.sub.21 to V.sub.23, respectively. It should be noted that the capacitor C15 corresponds to a parallel circuit constructed of the capacitors C11 and C12 (see FIG. 1).
As a preparation, a response is obtained in such a case that an electron charge "Q" is suddenly applied to the capacitor C15 of the circuit shown in FIG. 5(a). A voltage V.sub.10 (t) appearing across the terminals of the capacitor C15 is expressed by the following equation (1): EQU V.sub.10 (t)=(Q/C.sub.15) [1+A(.alpha.-.beta.).sup.-1 (AB+CD)](1)
wherein EQU C.sub.15 =C.sub.11 +C.sub.12 EQU A=C.sub.15 C.sub.13 R.sub.12 R.sub.13 EQU B=.alpha.exp (-.alpha.t) -.beta.exp (-.beta.t) EQU C=exp (-.alpha.t) -exp (-.beta.t)
Symbols ".alpha." and ".beta." are given by the following equations (2) and (3); EQU .alpha.={-e+(e.sup.2 -4A).sup.1/2 }/(2A) (2) EQU .beta.={-E-(E.sup.2 -4A).sup.1/2 }/(2A) (3) EQU wherein EQU E=C.sub.15 R.sub.12 +C.sub.13 R.sub.13 +C.sub.15 R.sub.13
The term "E.sup.2 -4A" in the above equations (2) and (3) is given as follows:
That is to say, assuming now: EQU G.sup.2 =(c.sub.15 R.sub.12 -C.sub.13 R.sub.13).sup.2 EQU H.sup.2 =(C.sub.15 /R.sub.13).sup.2 EQU I=C.sub.15 C.sub.13 R.sub.13 2 EQU J=C.sub.15 2R.sub.12 R.sub.13,
since G.sup.2 .gtoreq.O, H.sup.2 &gt;O, I&gt;O, J&gt;O, it is given EQU E.sup.2 -4A=G.sup.2 +H.sup.2 +2J+2J&gt;O
Symbols ".alpha." and ".beta." are real numbers.
Also, at this time, a voltage V.sub.20 (t) appearing across the terminals of the capacitor C13 is expressed by: EQU V.sub.20 (t)=[Q/(C.sub.15 C.sub.13 R.sub.12 R.sub.13)](.beta.-.alpha.).sup.-1 D (4)
Assuming now that the raising time instant "t" of the stepped waveform shown in FIG. 4(a) is equal to "O", when the sampling operation is carried out at a time instant "T" (T&gt;O) after the raising time of the stepped waveform, the circuit state immediately before the sampling operation is expressed by employing the above equations (1) and (4) as follows: EQU V.sub.11 =(C.sub.11 /C.sub.15)V.sub.10 T EQU V.sub.21 =(C.sub.11 /C.sub.15)V.sub.20 T
This circuit state is shown in FIG. 5(b).
Under this condition, if the sampling operation is performed in the track hold mode, the potential of the storage capacitor C12 becomes equal to the step voltage applied to the input terminal 56. On the other hand, the electron charges stored in the capacitor C13 are essentially neither charged nor discharged while the switch S11 is turned ON, assuming now that the ON-time period of the switch S11 is considerably shorter than the time constant C.sub.13, R.sub.13. As a consequence, it is assumed that the electron charges just before the switch S11 is turned ON for a short time period are reserved until the time "T" when the switch S11 is turned ON.
Assuming now that the amplitude of the stepped waveform applied to the input terminal 56 is equal to 1, the voltages V.sub.12 and V.sub.22 of the equivalent voltage sources V12 and V22 are given as follows: EQU V.sub.12 =1 EQU V.sub.22 =(C.sub.11 /C.sub.15)V.sub.20 (T)
This state is shown in FIG. 5(c).
The state of FIG. 5(c) may be expressed as a summation of FIGS. 5(d) and 5(e) with employment of the "principle of superposition", in which the voltages are given: EQU V.sub.13 =1-(C.sub.11 /C.sub.15)V.sub.10 (T) EQU V.sub.14 =(C.sub.11 /C.sub.15)V.sub.10 (T) EQU V.sub.13 =(C.sub.11 /C.sub.15)V.sub.20 (T)
Since the voltage response related to the resistor R.sub.13 shown in FIG. 5(e) is equal to such a response that no sampling operation is performed at the first sampling gate 11, it is given by: EQU V.sub.R13 =(C.sub.11 /c.sub.15)V.sub.20 (T)
As this response is coincident with the output response of the equivalent network 20 for correcting the "blowby" distortions, only a response by FIG. 5(d) appears at the output terminal of the differential amplifier 51B by canceling the response by FIG. 5(e).
The output response of FIG. 5(d) is obtained by employing the above equation (4) as follows: EQU V.sub.AB =[1-(C.sub.11/ C.sub.15)V.sub.10 (T)]V.sub.20 (t-T)(5)
The result is represented in FIG. 4(g).
In FIG. 4, it is now assumed that a time period from the operation of the switch S11 to the operation of the second sampling gate 55 is defined as "Ts", a sampling time instant "t" by the second sampling gate 55 is determined by: EQU t=T+Ts
Accordingly, when this time period "Ts" is introduced into the above equation (5), it is obtained:
V.sub.AB (RESULT)={1-(C.sub.11 /C.sub.15)V.sub.10 (T)}V.sub.20 (Ts)(6)
Although the above-described equation (6) represents the sampled output derived from the output terminal 59 (see FIG. 1), it indicates that it does not immediately become a constant value after the stepped waveform (see FIG. 4a) is raised at T=0. This is because the term [1-(C11/C15)V.sub.10 (T)] is dependent upon the time "T" contained in this equation. This may result in a waveform having such distortions as shown in FIG. 6(b) being reproduced with respect to an input of a stepped waveform of the signal source 50 shown in FIG. 6(a). It should be noted that rounded points shown in FIG. 6(b) indicate sampling points.
Since the first sampling gate 11 (see FIG. 1) has a leakage capacitance C11, the signal to be measured is leaked. The distortions caused by sampling it with the second sampling gate 55 can be canceled by the output derived from the equivalent network 20. However, in case of the track hold mode, distortions different from the first-mentioned distortions caused by this leakage signal, which is produced by sampling the input signal in the first sampling gate, are remarkably produced, whereby there is a problem that the waveform as represented in FIG. 6(b), which is different from the original waveform, is reproduced.
A major cause of an occurrence of such distortions in the reproduced waveform is that the above equation (6) owns the term V.sub.10 (T) depending on the time "T".